乔建民，生于1960年2月，杭州汉宇科技有限公司总经理。
　　乔博士1982年就读于浙江大学材料系；1989年获得罗马大学和浙江大学材料科学博士学位；1989年浙江大学材料系教师；1991年赴美在Santa Clara 大学做博士后研究，并与1992年创办美国高科技研究生教育的国际科技大学；1996年在美国的应用材料公司任资深工程经理；1998年任美国Cypress半导体公司研发总工程师；2000年创办美国先进光通信公司；2002年创办美国HQ科技公司；2004年出任美国PicoNetics公司运营总监；2005年回国，在杭州创办了汉力国际微电子有限公司2009年创办杭州汉宇科技有限公司。乔建民博士是材料工程学、微电子工程学专家，浙江省海创会副会长、浙江大学校友总会理事、浙江大学海创俱乐部常务副理事长，曾任美国北加州浙大校友会会长，在当地侨界有很大的影响力。他目前也是萧山开发区高级经济顾问。
　　乔博士1988年研发出的非晶硅太阳能电池的能量转换效率曾创造了欧洲最高记录, 并制造出了世界上第一只非晶硅高能粒子探测器。1990和1991年乔博士被我国国务院和国家教育部任命为作出杰出贡献的年轻科学家和优秀年轻教师。1994年至2000年在美学习工作期间，研发出了多项微电子工程创新技术, 1994年被美国政府认定为具有卓著能力的科学家。2001年至2008年研发出了多项纳米材料创新技术。2005年乔博士参与了以《基于能量回收原理的微电子超低功耗机理研究》为课题的国家973计划；同时乔博士拥有20个美国专利和多项欧洲日本和台湾专利。
　　1.纳米硅改性双组份耐磨渗透硬化剂及其制备方法。中国专利受理号：201410172177.X
　　2.仿大理石材料干粉及高光防滑仿大理石地坪的施工方法。中国专利受理号：201410171661.0
　　3.J. Chen, J. Chen; and J. Qiao, Semiconductor processing chamber substrate holder method and structure, US Patent#: 6,865,065, March 8, 2005.
　　4.W. Branco and J. Qiao, Method for cleaning plasma etch chamber structures, US Patent#: 6,841,008, January 11, 2005.
　　5.J. Qiao, S. Geha, and M.G. Sediegh, Method of forming self aligned contacts, US Patent#: 6,803,318, October 12, 2004.
　　6.B. Jin, J. Qiao and S. Sharifzadeh, Semiconductor structure and method of making contacts in a semiconductor structure, US Patent #: 6,734,108, May 11, 2004.
　　7.M.G. Sedigh, J. Qiao, and S. Geha, Method for etching a dielectric layer formed upon a barrier layer, US Patent #: 6,693,042, February 17, 2004.
　　8.A. Blosse, S. Thedki, J. Qiao, and Y. Gilboa, Method of making metallization and contact structures in an integrated circuit, US Patent #: 6,635,566, October 21, 2003.
　　9.Z. Wan, J. Chen; Jiong, P. Ling; Peiching, and J. Qiao, Apparatus and method for uniformly depositing thin films over substrates, US Patent #: 6,579,420, June 17, 2003.
　　10.A. Blosse, S. Thekdi, J. Qiao, and Y. Gilboa, Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer, US Patent #: 6,399,512, June 4, 2002; also European Patent #: EP1164637, December 19, 2001; also Japan Paten #: JP2002016140, January 18, 2002.
　　11.L. Murugesh, M. Orczyk, P. Narawankar, J. Qiao, and T. Sahin, Sequential in-situ heating and deposition of halogen-doped silicon oxide, US Patent #: 6,375,744, April 23, 2002.
　　12.J. Qiao, J. Nulty, P. Arleo, and S. Salimian, Electrostatic or mechanical chuck assembly conferring improved temperature uniformity onto workpieces held thereby, workpiece processing technology and/or apparatus containing the same, and method(s) for holding and/or processing a workpiece with the same, US Patent #: 6,373,679, April 16, 2002.
　　13.J. Qiao, S. Thekdi, M. Rathor, and J. Nulty, Plasma-etch chemistry and method of improving etch control, US Patent #: 6,372,634, April 16, 2002.
　　14.B. Jin and J. Qiao, Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device, US Patent #: 6,350,665, February 26, 2002.
　　15.S. Thekdi, A. Blosse, Y. Gilboa, and J. Qiao, Method of making metallization and contact structures in an integrated circuit, European Patent #: EP1168434, February 1, 2002; also Japan Patent #: JP2002016139, January 18, 2002.
　　16.J. Qiao and S. Thekdi, Method for conditioning a plasma etch chamber, US Patent #: 6,322,716, November 27, 2001.
　　17.L. Murugesh, M. Orczyk, P. Narawankar, J. Qiao, and T. Sahin, Sequential in-situ heating and deposition of halogen-doped silicon oxide, US Patent #: 6,228,781, May 8, 2001.
　　18.J. Qiao and J. Nulty, Method and structure for making self-aligned contacts, US Patent #: 6,214,743, April 10, 2001.
　　19.P. Narwankar, L. Murugesh, T. Sahin, M. Orczyk, and J. Qiao, High deposition rate recipe for low dielectric constant films, US Patent #: 6,136,685, October 24, 2000; also Japan Patent #: JP10340900, December 22, 1998.
　　20.J. Qiao and J. Feng, Method of reducing impurity contamination in semiconductor process chambers, US Patent #: 5,976,900, November 2, 1999.
　　21.J. Zhao, T. Cho, X. Guo, A. Tabata, J. Qiao, and A. Schreiber, Method of reducing residue accumulation in CVD chamber using ceramic lining, US Patent #: 5,885,356, March 23, 1999, also European Patent #: EP0780490, June 25, 1997; also Japan Patent #: JP9251992, September 22, 1997.
　　22.J. Qiao, C. Chan, C. Leung, D. Chan, and T. Sahin, Method and apparatus for seasoning a substrate processing chamber, Taiwan Patent #: TW416100; also European Patent #: EP0892083, January 19, 1999; also Japan Patent #: JP11067746, March 9, 1999.